![]() This analysis shows that the number to put on a set_input_delay -max constraint is the maximal clock-to-output of the external device that drives the input pin ( + the trace delay of the board). All in all, the clock path ends at 22.129 ns, which is 15.664 ns after the data arrived to the flip-flop. This calculation also takes the estimated jitter into account (by virtue of "clock uncertainty"). The clock travels from the input pin to the flip-flop (with no compensation for the clock network delay, since no PLL is involved). Once again, the values of the delays are chosen from the fastest possible combination. The clock path is then calculated, starting from the following clock at 20 ns. Together with the FPGA’s own data path delay (2.465 ns), the total data path delay stands at 6.465 ns. The values that are used for the delays of the logic elements are those of the fastest possible combination of process, voltage and temperature. It then adds the 4 ns (clock-to-output) that was specified in the max input delay constraint, and continues that data path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s)ĪE20 IBUF (Prop_ibuf_I_O) 0.291 4.291 r test_in_IBUF_inst/O ![]() Path Type: Setup (Max at Fast Process Corner) (rising edge-triggered cell FDRE clocked by theclk period=20.000ns}) (input port clocked by theclk period=20.000ns}) Set_input_delay -clock theclk -min 2 Analysis of set_input_delay -max (setup) Slack (MET) : 15.664ns (required time - arrival time) In accordance with that other post, the timing constraints behind the examples below are: create_clock -name theclk -period 20 This page is the example part of another post, which explains the meaning of set_input_delay and set_output_delay in SDC timing constraints.
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